ACCEL

Description

The goal of this project is to build an end-to-end FPGA accelerator for CNN inference.

The team will design a parameterized systolic-array architecture that uses FPGA DSP slices for parallel multiply-accumulate operations and BRAM for storing weights, activations, and intermediate results.

On top of the hardware accelerator, the project will develop:

• A hardware-aware compiler or model conversion pipeline that maps PyTorch models onto the accelerator
• A lightweight host CPU runtime for transferring data, configuring the FPGA, and running inference
• A benchmark suite to evaluate latency, throughput, resource utilization, accuracy, and potentially power consumption

The final system should demonstrate the complete workflow from a trained PyTorch CNN, such as a CIFAR-10 classifier, to inference running on custom FPGA hardware.

The project combines digital hardware design, machine learning, compiler development, and systems programming, allowing team members to specialize in different parts of the stack.

Expected duration: 6–8 months part-time